2.3.7. CPU 2.3.7.1. Introduction The 4502, upon reset, looks and acts like any other CMOS 6502 processor, with the exception that many instructions are shorter or require less cycles than they used to. This causes programs to execute in less time that older versions, even at the same clock frequency. The, stack pointer has been expanded to 16 bits, but can be used in two different modes. It can be used as a full 16-bit (word) stack pointer, or as an 8-bit (byte) pointer whose stack page is programmable. On reset, the byte mode is selected with page 1 set as the stack page. This is done to make it fully 65C02 compatible. The zero page is also programmable via a new register, the "B" or "Base Page" register. On reset, this register is cleared, thus giving a true "zero" page for compatability reasons, but the user can define any page in memory as the "zero" page. A third index register, "Z", has been added to increase flexibility in data manipulation. This register is also cleared, on reset, so that the STZ instructions still do what they used to, for compatibility. This is a list of opcodes that have been added to the 210 previously defined MOS, Rockwell, and GTE opcodes. 1. Branches and Jumps BCC label word-relative BCS label word-relative BEQ label word-relative BMI label word-relative BNE label word-relative BPL label word-relative BRA label word-relative BVC label word-relative BVS label word-relative BSR label Branch to subroutine (word relative) JSR (ABS) Jump to subroutine absolute indirect JSR (ABS,X) Jump to subroutine absolute indirect, X RTN # Return from subroutine and adjust stack pointer 2. Arithmetic Operations NEG A Negate (or 2's complement) accumulator ASR A Arithmetic Shift right accumulator or memory ASR ZP ASR ZP,X INW ZP Increment Word DEW ZP Decrement Word INZ Increment and DEZ Decrement Z register ASW ABS Arithmetic Shift Left Word ROW ABS Rotate Left Word ORA (ZP),Z These were formerly (ZP) non-indexed AND (ZP),Z now are indexed by Z register EOR (ZP),Z (when .Z=0, operation is the same) ADC (ZP),Z CMP (ZP),Z SBC (ZP),Z CPZ IMM Compare Z register with memory immediate, CP2 ZP zero page, and CPZ ABS absolute. 3. Loads, Stores, Pushes, Pulls and Transfers LDA (ZP),Z formerly (ZP) LDZ IMM Load Z register immediate, LDZ ABS absolute, LDZ ABS,X absolute,X. LDA (d,SP),Y Load Accu via stack vector indexed by Y STA (d,SP),Y and Store STX ABS,Y Store X Absolute,Y STY ABS,X Store Y Absolute,X STZ ZP Store Z register (formerly store zero) STZ ABS STZ ZP,X STZ ABS,X STA (ZP),Z formerly (ZP) PHD IMM Push Data Immediate (word) PHD ABS Push Data Absolute (word) PHZ Push Z register onto stack PLZ Pull Z register from stack TAZ Transfer Accumulator to Z register TZA Transfer Z register to Accumulator TAB Transfer Accumulator to Base page register TBA Transfer Base page register to Accumulator TSY Transfer Stack Pointer High byte to Y register and set "byte" stack-pointer mode TYS Transfer Y register to Stack Pointer High byte and set "word" stack-pointer mode 2.3.7.2. CPU Operation The 4502 has the following 8 user registers: A accumulator X index-X Y index-Y Z index-Z B Base-page P Processor status SP Stack pointer PC Program counter Accumulator The accumulator is the only general purpose computational register. It can be used for arithmetic functions add, subtract, shift, rotate, negate, and for Boolean functions and, or, exclusive-or, and bit operations. It cannot, however, be used as an index register. Index X The index register X has the largest number of opcodes pertaining to, or using it. It can be incremented, decremented, or compared, but not used for arithmetic or logical (Boolean) operations. It differs from other index registers in that it is the only register that can be used in indexed-indirect or (bp,X) operations. It cannot be used in indirect-indexed or (bp),Y mode. Index Y The index register Y has the same computational constraints as the X register, but finds itself in a lot less of the opcodes, making it less generally used. But the index Y has one advantage over index X, in that it can be used in indirect-indexed operations or (bp),Y mode. Index Z The index register Z is the most unique, in that it is used in the smallest number of opcodes. It also has the same computation limitations as the X and Y registers, but has an extra feature. Upon reset, the Z register is cleared so that the STZ (store zero) opcodes and non-indexed indirect opcodes from previous 65C02 designs are emulated. The Z register can also be used in indirect-indexed or (bp),Z operations. Base page B register Early versions of 6502 microprocessors had a special subset of instructions that required less code and less time to execute. These were referred to as the "zero page" instructions. Since the addressing page was always known, and known to be zero, addresses could be specified as a single byte, instead of two bytes. The CSG4502 also implements this same "zero page" set of instructions, but goes one step further by allowing the programmer to specify which page is to be the "zero page". Now that the programmer can program this page, it is now, not necessarily page zero, but instead, the "selected page". The term "base page" is used, however. The B register selects which page will be the "base page", and the user sets it by transferring the contents of the accumulator to it. At reset, the B register is cleared, giving initially a true "zero page". Processor status P register The processor status register is an 8-bit register which is used to indicate the status of the microprocessor. It contains 8 processor "flags". Some of the flags are set or reset based on the results of various types of operations. Others are more specific. The flags are... Flag Name Typical indication N Negative result of operation is negative V Overflow result of add or subtract causes signed overflow E Extend disables stack pointer extension B Break interrupt was caused by BRK opcode D Decimal perform add/subtract using BCD math I Interrupt disable IRQ interrupts Z Zero result of Operation is zero C Carry operation caused a carry Stack Pointer SP The stack pointer is a 16 bit register that has two modes. It can be programmed to be either an 8-bit page programmable pointer, or a full 16-bit pointer. The processor status E bit selects which mode will be used. When set, the E bit selects the 8-bit mode. When reset, the E bit selects the 16-bit mode. Upon reset, the CSG 4502 will come up in the 8-bit page- programmable mode, with the stack page set to 1. This makes it compatible with earlier 6502 products. The programmer can quickly change the default stack page by loading the Y register with the desired page and transferring its contents to the stack pointer high byte, using the TYS opcode. The 8-bit stack pointer can be set by loading the X register with the desired value, and transferring its contents to the stack pointer low byte, using the TXS opcode. To select the 16-bit stack pointer mode, the user must execute a CLE (for CLear Extend disable) opcode. Setting the 16-bit pointer is done by loading the X and Y registers with the desired stack pointer low and high bytes, respectively, and then transferring their contents to the stack pointer using TXS and TYS. To return to 8-bit page mode, simple execute a SEE (SEt Extend disable) opcode. ************************************************************* * WARNING * * * * If you are using Non-Maskable-Interrupts, or Interrupt * * Request is enabled, and you want to change BOTH stack * * pointer bytes, do not put any code between the TXS and * * TYS opcodes. Taking this precaution will prevent any * * interrupts from occuring between the setting of the two * * stack pointer bytes, causing a potential for writing * * stack data to an unwanted area. * ************************************************************* Program Counter PC The program counter is a 16-bit up-only counter that determines what area of memory that program information will be fetched from. The user generally only modifies it using jumps, branches, subroutine calls, or returns. It is set initially, and by interrupts, from vectors at memory addresses FFFA through FFFF (hex). See "Interrupts" below. 2.3.7.3. 65CE02 Interrupts There are four basic interrupt sources on the CSG 4502. These are RES*, IRQ*, NMI*, and SO, for Reset, Interrupt Request, Non-Maskable Interrupt, and Set Overflow. The Reset is a hard non-recoverable interrupt that stops everything. The IRQ is a "maskable" interrupt, in that its occurance can be prevented. The MMI is "non-maskable", and if such an event occurs, cannot be prevented. The SO, or Set Overflow, is not really an interrupt, but causes an externally generated condition, which can be used for control of program flow. One important design feature, which must be remembered is that no interrupt can occur immediately after a one-cycle opcode. This is very important, because there are times when you want to temporarily prevent interrupts from occurring. The best example of this is, when setting a 16-bit stack pointer, you do not want an interrupt to occur between the times you set the low-order byte, and the high-order byte. If it could happen, the interrupt would do stack writes using a pointer that was only partially set, thus, writing to an unwanted area. IRQ* The IRQ* (Interrupt ReQuest) input will cause an interrupt, if it is at a low logic level, and the I processor status flag is reset. The interrupt sequence will begin with the first SYNC after a multiple-cycle opcode. The two program counter bytes PCH and PCL, and the processor status register P, are pushed onto the stack. (This causes the stack pointer SP to be decremented by 3.) Then the program counter bytes PCL and PCH are loaded from memory addresses FFFE and FFFF, respectively. An interrupt caused by the IRQ* input, is similar to the BRK opcode, but differs, as follows. The program counter value stored on the stack points to the opcode that would have been executed, had the interrupt not occurred. On return from interrupt, the processor will return to that opcode. Also, when the P register is pushed onto the stack, the B or "break" flag pushed, is zero, to indicate that the interrupt was not software generated. NMI* The NMI* (Non-Maskable Interrupt) input will cause an interrupt after receiving high to low transition. The interrupt sequence will begin with the first SYNC after a multiple-cycle opcode. NMI* inputs cannot be masked by the processor status register I flag. The two program counter bytes PCH and PCL, and the processor status register P, are pushed onto the stack. (This causes the stack pointer SP to be decremented by 3.) Then the program counter bytes PCL and PCH are loaded from memory addresses FFFA and FFFB. As with IRQ*, when the P register is pushed onto the stack, the B or "break" flag pushed, is zero, to indicate that the interrupt was not software generated. RES* The RES* (RESet) input will cause a hard reset instantly as it is brought to a low logic level. This effects the following conditions. The currently executing opcode will be terminated. The B and Z registers will be cleared. The stack pointer will be set to "byte" mode/with the stack page set to page 1. The processor status bits E and I will be set. The RES* input should be held low for at least 2 clock cycles. But once brought high, the reset sequence begins on the CPU cycle. The first four cycles of the reset sequence do nothing. Then the program counter bytes PCL and PCH are loaded from memory addresses FFFC and FFFD, and normal program execution begins. SO The SO (Set Overflow) input does, as its name implies, set the overflow or V processor status flag. The effect is immediate as this active low signal is brought or held at a low logic level. Care should be taken if this signal is used, as some of the opcodes can set or reset the overflow flag, as well. NOTE: The SO pin has been removed for C65.